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HM658128A series 131072-word 8-bit high speed cmos pseudo static ram rev. 8.0 jun. 5, 1995 the hitachi HM658128A is a pseudo-static ram organized as 131,072-word 8-bit. HM658128A realizes low power consumption and high speed access time by employing 1.3 ? cmos process technology. the HM658128A supports 3 refresh functions: address refresh, auto refresh and self refresh. low power version dissipates only 350 ? (typ)/500 ? (typ) in self refresh mode and retains the data with battery. the HM658128A is pin-compatible with 1-mbit static ram. features single 5 v ( 10%) high speed access time ce access time: 80/100/120 ns cycle time random read/ write cycle time: 130/160/190 ns low power: active: 300 mw (typ) standby: 350 ? (typ) (ll-version) 500 ? (typ) (l-version) all inputs and outputs ttl compatible non multiplexed address 512 refresh cycles (8 ms) refresh functions address refresh automatic refresh self refresh ordering information access type no. time package HM658128Alp-8 80 ns 600-mil 32-pin HM658128Alp-10 100 ns plastic dip HM658128Alp-12 120 ns (dp-32) HM658128Alp-8l 80 ns HM658128Alp-10l 100 ns HM658128Alp-12l 120 ns HM658128Alfp-8 80 ns 32-pin plastic HM658128Alfp-10 100 ns sop (fp-32d) HM658128Alfp-12 120 ns HM658128Alfp-8l 80 ns HM658128Alfp-10l 100 ns HM658128Alfp-12l 120 ns HM658128Alt-8 80 ns 8 mm 20 mm HM658128Alt-10 100 ns 32-pin plastic HM658128Alt-12 120 ns tsop HM658128Alt-8l 80 ns (tfp-32d) HM658128Alt-10l 100 ns HM658128Alt-12l 120 ns HM658128Alr-8 80 ns 8 mm 20 mm HM658128Alr-10 100 ns 32-pin plastic HM658128Alr-12 120 ns tsop HM658128Alr-8l 80 ns reverse type HM658128Alr-10l 100 ns (tfp-32dr) HM658128Alr-12l 120 ns ade-203-188h(z)
2 HM658128A series pin arrangement a15 a0 31 1 rfsh 2 a16 3 a14 4 a12 5 a7 6 a6 7 a5 8 a4 9 a3 10 a2 11 a1 12 13 14 i/o 1 i/o 0 v cc 32 cs 30 we 29 a13 28 a8 27 a9 26 a11 25 oe 24 a10 23 ce 22 i/o 7 21 i/o 6 20 19 15 i/o 2 i/o 5 18 16 v ss i/o 4 i/o 3 17 HM658128Alp/alfp series HM658128Alt series (top view) a10 a12 31 1 a11 2 a9 3 a8 4 a13 5 we 6 cs 7 a15 8 v cc 9 rfsh 10 a16 11 a14 12 13 14 a6 a7 oe 32 ce 30 i/o 7 29 i/o 6 28 i/o 5 27 i/o 4 26 i/o 3 25 v ss 24 i/o 2 23 i/o 1 22 i/o 0 21 a0 20 19 15 a5 a1 18 16 a4 a2 a3 17 (top view)
pin arrangement (cont) pin description symbol pin name a0 to a16 address inputs i/o0 to i/o7 data input/output rfsh refresh ce chip enable oe output enable we write enable cs chip select v cc power supply v ss ground 3 HM658128A series cc a3 a2 a1 a0 i/o0 i/o1 i/o2 v i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 oe ss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a4 a5 a6 a7 a12 a14 a16 rfsh v a15 cs we a13 a8 a9 a11 (top view) HM658128Alr series
4 HM658128A series block diagram truth table ce cs at ce going low rfsh oe we i/o pin mode lh x* 1 l h low-z read l h x x l high-z write l h x h h high-z l l x x x high-z cs standby h x l x x high-z refresh h x h x x high-z standby notes: 1. x means h or l. memory matrix (512 256) 8 row de- coder address latch control a0 a8 i/o 0 i/o 7 input data control column i/o column decoder address latch control a9 a16 refresh control rfsh ce cs oe we timing pulse generator read/write control
5 HM658128A series absolute maximum ratings parameter symbol rating unit terminal voltage with respect to v ss v t ?.0 to +7.0 v power dissipation p t 1.0 w operating temperature topr 0 to +70 ? storage temperature tstg ?5 to +125 ? storage temperature under bias tbias ?0 to +85 ? recommended dc operating conditions (ta = 0 to +70?) parameter symbol min typ max unit note supply voltage v cc 4.5 5.0 5.5 v v ss 000v input voltage v ih 2.2 6.0 v v il ?0.5 0.8 v 1 note: 1. v il min = ?.0 v for pulse width 10 ns.
6 HM658128A series dc characteristics (ta = 0 to +70?, v cc = 5 v 10%) parameter symbol min typ max unit test conditions notes operating power i cc1 ?0 85mai i/o = 0 ma supply current t cyc = min. standby power i sb1 ? 2 ma ce = v ih supply current rfsh = v ih , vin 3 0 v standby power i sb2 100 200 ? ce 3 v cc ?.2 v 1 supply current rfsh 3 v cc ?.2 v, vin 3 0 v 70 100 ? ce 3 v cc ?.2 v 2 rfsh 3 v cc ?.2 v, vin 3 0 v operating power i cc2 ? 2 ma ce = v ih 1, 2 supply current in rfsh = v il , vin 3 0 v self refresh mode i cc3 100 200 ? ce 3 v cc ?.2 v 1 rfsh 0.2 v, vin 3 0 v 70 100 ? ce 3 v cc ?.2 v 2 rfsh 0.2 v, vin 3 0 v input leakage i li ?0 10 a v cc = 5.5 v current vin = v ss to v cc output leakage i lo ?0 10 a oe = v ih current v i/o = v ss to v cc output voltage v ol 0.4 v i ol = 2.1 ma v oh 2.4 v i oh = ? ma notes: 1. this characteristics is guaranteed only for l-version. 2. this characteristics is guaranteed only for ll-version. capacitance (ta = 25?, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance cin 8 pf vin = 0 v input/output capacitance c i/o ?0pfv i/o = 0 v note: this parameter is sampled and not 100% tested.
7 HM658128A series ac characteristics (ta = 0 to +70?, v cc = 5 v 10%) test conditions input pulse levels: 2.4 v, 0.4 v input rise and fall times: 5 ns timing measurement level: 2.2 v, 0.8 v reference level: v oh = 2.0 v, v ol = 0.8 v output load: 1 ttl and 100 pf (including scope and jig) HM658128A -8 -10 -12 parameter symbol min max min max min max unit note random read or write cycle time t rc 130 160 190 ns random read-modify-write t rwc 190 220 260 ns cycle time chip enable access time t cea 80 100 120 ns output enable access time t oea 30 30 40 ns chip disable to output in high-z t chz 0 30 0 30 0 35 ns 1, 2 chip enable to output in low-z t clz 20 20 20 ns 2 output disable to output in high-z t ohz 25 25 30 ns 1, 2 output enable to output in low-z t olz 0 0 0 ns 2 chip enable pulse width t ce 80 n 10 100 n 10 120 n 10 s chip enable precharge time t p 40 50 60 ns address setup time t as 0 0 0ns address hold time t ah 30 30 35 ns read command setup time t rcs 0 0 0ns read command hold time t rch 0 0 0ns rfsh hold time t rhc 15 15 15 ns rfsh delay time for standby t rcd 5 5 5 ns 10 chip select setup time t css 0 0 0ns chip select hold time t csh 30 30 35 ns write command pulse width t wp 30 30 35 ns chip enable to end of write t cw 80 100 120 ns data in to end of write t dw 25 25 30 ns data in hold time for write t dh 0 0 0ns output active from end of write t ow 5 5 5 ns 2 write to output in high-z t whz 25 25 30 ns 1, 2 transition time (rise and fall) t t 350350350ns6
8 HM658128A series ac characteristics (ta = 0 to +70?, v cc = 5 v 10%) (cont) HM658128A -8 -10 -12 parameter symbol min max min max min max unit note refresh command delay time t rfd 40 50 60 ns refresh precharge time t fp 40 40 40 ns refresh command pulse width t fap 80 n 8 80 n 8 80 n 8 s for automatic refresh automatic refresh cycle time t fc 130 160 190 ns refresh command pulse width t fas 8 8 8s for self refresh refresh reset time for self t rfs 130 160 190 ns refresh refresh reset time for auto t rfa 0 0 0ns refresh refresh period (512 cycles) t ref ? 8 8 ms notes: 1. t chz , t ohz and t whz are defined as the time at which the output achieves the open circuit conditions. 2. t chz , t clz , t ohz , t olz , t whz and t ow are sampled under the condition of t t = 5 ns and not 100% tested. 3. a write occurs during the overlap of a low ce and a low we . write ends at the earlier of we going high or ce going high. 4. if the ce low transition occurs simultaneously with or latter from the we low transition, the output buffers remain in high impedance state. 5. in write cycle, oe or we must disable output buffers prior to applying data to the device and at the end of write cycle data inputs must be floated prior to oe or we turning on output buffers. 6. transition time t t is measured between v ih min and v il max. 7. after power-up, pause more than 100 ? and execute at least 8 initialization cycles. 8. 512 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed within 15 ? after self refresh, in order to meet the refresh specification of 8 ms and 512 cycles. 9. at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and rfsh must be kept high. if auto refresh follows self refresh, low transition of rfsh at the beginning of auto refresh must not occur during t rfs period. 10. if t p is larger than 60 ns, t rcd can be 8 ? maximum.
9 HM658128A series timing waveforms read cycle t ce t rc t p t css t csh t as t ah t rcs t rch t cea t rcd t oea t rhc t olz t clz valid data out t chz t ohz cs address a0?16 dout oe ce we rfsh valid
10 HM658128A series write cycle 1 ( oe clock) t ce t rc t p t css t csh t as t ah cs address a0?16 ce t cw t wp t rcd t rhc t dw t dh t ow t chz t olz t clz t ohz t whz we oe rfsh din dout valid data valid
11 HM658128A series write cycle 2 ( oe low fix) t ce t rc t p t css t csh t as t ah cs address a0?16 ce t cw t wp t rcd t rhc rfsh t dh t clz t whz we oe din dout t dw valid data in valid
12 HM658128A series read-modify-write cycle t rwc t p t css t csh t as t ah cs address a0?16 ce t wp t rcs t rch we t rhc rfsh t ohz t rcd t dw t oea t dh valid data in t olz t cea t chz t ow t whz valid data out t clz oe din dout valid
13 HM658128A series auto refresh cycle self refresh cycle cs standby mode t rfd t fc t fc t rcd t fap t fp t fap ce rfsh t rfa t rfd t rcd t fas t rfs rfsh t rhc ce t p t rc t ce t css t csh ce cs
14 HM658128A series package dimensions HM658128Alp series (dp-32) unit: mm HM658128Alfp series (fp-32d) unit: mm 0.51 min 2.54 min 5.08 max 0.25 + 0.11 ?0.05 2.54 ?0.25 0.48 ?0.10 0??15 41.9 42.5 max 13.4 13.7 max 1.2 15.24 32 17 1 16 2.3 max 0.15 0 ?8 ? m + 0.10 ?0.05 0.40 20.45 1.0 max 1.27 11.7 max 1.42 0.8 3.0 max 0.05 min 0.22 + 0.13 ?0.07 20.95 max 32 17 1 16 14.14 ?0.30 0.10
15 HM658128A series package dimensions (cont) HM658128Alt series (tfp-32d) unit: mm HM658128Alr series (tfp-32dr) unit: mm 0.10 0.08 m 0.5 8.0 0.2 ?0.1 20.0 ?0.2 0.17 ?0.05 0.08 min 0.18 max 1.2 max 18.4 0 ?5 ? 32 116 17 8.2 max 0.45 max 0.5 ?0.1 0.10 0.08 m 0.50 8.0 0.20 ?0.10 20.0 ?0.2 0.17 ?0.05 0.08 min 0.18 max 1.20 max 18.40 0 ?5 ? 17 16 1 32 8.2 max 0.50 ?0.10 0.45 max

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